INTEL 8255 Programmable Peripheral Interface (PART-2)

Internal block diagram of 8255

The ports are grouped as Group A and Group B. The group A has port A, port C upper and its control circuit. The group B has port B, port C lower and its control circuit. The Read/Write control logic requires six control signals. These signals are given below.

RD (Read) :   This control signal enables the read operation.
                     When this signal is LOW, the microprocessor reads data from a selected I/O port of the 
                      8255A.

WR (Write):  This control signal enables the write operation.
                       When this signal goes LOW, the microprocessor writes into a selected I/O port
                       or the control register.

RESET:         This is an active HIGH signal.
                       It clears the control register and set all ports in the input mode.

CS, A0  and A1 : These are device select signals.
                             The CS is connected to the decoder in the system.
                             A0 and A1 are generally connected to A0 and A1 of the processor.

(Alternatively, A0 and A1 can be connected to any two-address lines of the processor).
8255 can be either Memory mapped or I/O mapped in the system.

A0 and A1 address lines can be made to select any one of the following four internal devices as shown on right side.

Programming 8255:
The 8255 has two control words, one for specifying 1/O functions and another for bit set/reset mode of port C. Both the control words are written in the same control register.

The control register differentiate them by the value of bit D7 .The bit set/reset control word does not affect the functions of ports A and B.

Bit D7 of the control register specifies either the 1/0 function or the bit set / reset function.
If bit D7 = 1, then the bits D6 – D0 determine 1/0 functions in various modes.
If bit D7 = 0, then the bits D6 – D0 determine the pin of port C to be set or reset.


The 8255 ports are programmed (or initialized) by writing a control word in the control register.

For setting 1/0 functions and mode of operation the 1/0 mode control word is send to control register. The format of the 1/0 mode set control word is shown below.

For setting/resetting (BSR mode) a pin of port C, the bit set/ reset control word is sent to control register. The format of bit set/reset control word is shown below.

 

The data transfer between the processor and the port can be either interrupt driven or through status check.

In the interrupt driven data transfer scheme, when the port is ready, it interrupts the processor for a read or write operation.

In status check technique, the processor polls the status of the port and checks whether the port is ready for data transfer or not. The status of the ports A and B can be known by reading the port C. When the port is ready for data transfer, the processors executes a read or write cycle.

INTEL 8255 Programmable Peripheral Interface (PART-1)

Intel 8255 is a programmable peripheral interface chip designed for parallel communication between microprocessor and I/O devices, which have a speed mismatch between each other.


Features of 8255:

•It has three 8-bit ports
•It can be operated in three different modes in I/O mode and in BSR mode

IC 8255 has three ports A, Band C. The ports A and B are 8 bit parallel ports. Port A can be programmed to work in any one of the three modes as input or output port. The three operating modes are

Mode-0  - Simple I/O port
Mode-l   - Handshake I/O port
Mode-2  - Bidirectional I/O port.

The port B can be programmed to work either in mode-0 or mode-1. The port C pins (8-pins) have different assignments depending on the mode of port A and B. If port A and B are programmed in mode-0, then the port C can perform anyone of the following function.

1. As 8 bit parallel port in mode-0 for input or output.
2. As two numbers of 4 bit parallel port in mode-O for input or output.
3. The individual pins of port C can be set or reset for various control applications.

The various functions (assignments) of port C during the different operating modes of port A and B are listed in Table below.

If ports A and Bare programmed in mode-l or mode-2, then some of the pins of port C are used for handshake signals and the remaining pins can be used as input/output lines or individually set/reset for control applications.



I/0 Modes of 8255

Mode-0: In this mode, all the three ports can be programmed either as input or output port. In mode-O, the outputs are latched and the inputs are not latched. The ports do not have handshake or Interrupt capability. The ports in mode-o can be used to interface DIP switches, Hexa-keypad, LED's and 7-segment LED's to the processor.

Mode-l: In this mode, only ports A & B can be programmed either as input or output port. In mode-1, handshake signals are exchanged between the processor and peripherals prior to data transfer. The port C pins are used for  handshake signals. Input and output data are latched. Interrupt driven data transfer scheme is possible.

8255 Handshake Input port (Mode 1)

8255 Handshake Output port (Mode 1)\

Mode-2: In this mode, the port will be a bi-directional port (i.e., the processor can perform both read and write operations with an I/O device connected to a port in mode-2).
Only port-A can be programmed to work in mode-2. Five pins of port C are used for handshake signals. This mode is used primarily in applications such as data transfer between two computers or floppy disk controller interface.

Pins & Signals of 8255

The pin description of 8255 is shown in figure below. It has 40 pins and requires a single +5V supply.

INTEL 8085 Processor - Question & Answers (part-2)

In  a microprocessor system using  8085,  the  memory  requirement  is 8kb  EPROM  and 8kb  RAM.  For  interfacing  I/O  devices,  three  numbers  of  8255  are  required.  Select suitable memories and explain how they are interfaced to the system. Interface the 8255 by memory mapping.?

    The IC 2764 is selected for EPROM memory and the IC 6264 is selected for RAM memory.
    Both the memory lC have time compatibility with 8085 processor.
    The  8kb  EPROM,  2764  require  13  address  tines.  The  8kb  RAM,  6264  require  13  address lines.
    The address lines A0 to A12  are connected to both EPROM and RAM memory ICs.
    The 8255 require four internal addresses.

    Let us connect A1  of 8085 to A0  of 8255 and A2  of 8085 to A1  of 8255.
    The 8255 is memory mapped in the system.
    For  the  memories  and  8255’ s we  require  5  chip-select  signals.  Hence  we  can  use  a  3-to-8 decoder  74LS138  for  generating  eight  chip-select  signals  by  decoding  the  unused  address lines A13, A14  and A15.
    The decoder enable pins are permanently tied to appropriate levels. In the eight chips select
signals five are used for selecting memory ICs and 8255, and the remaining three can be used for future expansion.
    The EPROM is mapped at the starting of memory space. The RAM is mapped at the end of memory space. The EPROM is  mapped  from 0000H to IFFFH. The RAM is  mapped from E000H to FFFFH.
    The  four  internal devices of 8255 are control register, port-A,  port-B and  port-C.  A 16-bit address is allotted to each internal device of 8255.

Memory and I/O Port Interfacing with 8085

The 16 bit address for the memory and 8255 devices are,

A  system  requires  16kb  EPROM  and  16kb  RAM.  Also  the  system  has  2  numbers  of 8255, one number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral  interface;  8279-Keyboard/display  controller,  8251  –  USART  and  8254  -  Timer). Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.

• The  I/O  devices  in  the  system  should  be  mapped  by  standard  I/O  mapping.  Hence  separate decoders can be used to generate chip select signals for memory IC and peripheral IC’ s.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.

• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.

• The  8kb  memories  require  13  address  lines.  Hence  the  address  lines  A0   –  A12   are  used  for selecting the memory locations.
• The unused address lines A13, A14  and A15  are used as input to decoder 74LS138 (3-to-8-deeoder)

of memory IC.  The  logic  low  enables of this decoder are tied to  IO/ M(low) of 8085,  so that this decoder  is  enabled  for  memory read/write  operation.  The  other  enable  pins  of decoder  are tied  to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and
the remaining 4 are kept for future expansion.

• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.

•  The RAM is mapped at the end of memory space from C000 to FFFFH.

• There are five peripheral IC’ s to be interfaced to the system. The chip-select signals for these IC’ s

are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12  and A13
• The address lines A13, A14  and A15  are logically ORed and applied to low enable of I/O decoder.

• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.

Memory and I/O Port Interfacing with 8085

INTEL 8085 Processor - Question & Answers (part-1)

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.

• The memory capacity is 64 Kbytes. i.e
          2 n = 64 x 1000 bytes where n = address lines. So, n = 16.

• In this  system the entire 16  address  lines of the processor are connected to  address input pins of memory IC in order to address the internal locations of memory.

• The  chip  select  (CS)  pin  of  EPROM  is  permanently  tied  to  logic  low  (i.e.,  tied  to ground).

• Since the processor  is connected to EPROM, the active  low  RD pin  is connected to active low output enable pin of EPROM.

• The range of address for EPROM is 0000H to FFFFH.

Interfacing 64Kb EPROM with 8085

Consider a system in which the available 64kb memory space is equally divided between
EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

•    Implement 32kb memory capacity of EPROM using single IC 27256.

•    32kb RAM capacity is implemented using single IC 62256.

•    The 32kb memory requires 15 address lines and so the address lines A0  – A14  of the processor are connected to 15 address pins of both EPROM and RAM.

•    The unused address line A15  is used as to chip select. If A15  is 1, it select RAM and If
A15  is 0, it select EPROM.

•    Inverter is used for selecting the memory.

•    The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively.

•    The  address  range  of  EPROM  will  be  0000H  to  7FFFH  and  that  of  RAM  will  be
7FFFH to FFFFH.

Interfacing 32Kb EPROM and 32Kb RAM with 8085

Consider a system in which 32kb memory space is implemented using four numbers of
8kb memory. Interface the EPROM and RAM with 8085 processor.

•    The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM.

•    Each 8kb memory requires 13 address lines and so the address lines A0- A12  of the processor are connected to 13 address pins of all the memory.

•    The address lines and A13  – A14  can be decoded using a 2-to-4 decoder to generate four chip select signals.

•    These  four chip  select  signals can  be used to  select  one of the  four  memory IC at  any one time.

•    The address line A15  is used as enable for decoder.

•    The simplified schematic memory organization is shown

Interfacing 16Kb EPROM and 16Kb RAM with 8085

•    The address allotted to each memory IC is shown in following table.

There are two types for interfacing I/O devices:

1.   Memory mapped I/O device.
2.   Standard I/O mapped I/O device or isolated I/O mapping.

DECODER IN 8085 PROCESSOR

It is used to select the memory chip of processor during the execution of a program.

No of IC used for decoder is,

•   2-4 decoder (74LS139)
•   3-8 decoder (74LS138)

TYPICAL EPROM AND STATIC RAM

A typical semiconductor memory IC will have n address pins, m data pins (or output pins).

•Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).

•The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).

•The  control signals  needed  for  read  operation  in  EPROM are  chip  select  (chip  enable)  and read control (output enable).

STRING INSTRUCTIONS IN 8086 PROCESSORS

• REP / REPE / REPZ / REPNE / REPNZ
• MOVS / MOVSB / MOVSW
• CMPS / CMPSB / CMPSW
• SCAS / SCASB / SCASW
• LODS / LODSB / LODSW
• STOS / STOSB / STOSW

ADDRESSING MODES:

1. Addressing modes for accessing immediate and register data.
2. Addressing modes for accessing data in memory.
3. Addressing modes for accessing I/O ports.
4. Relative Addressing mode.
5. Implied Addressing mode.

(1). Addressing modes for accessing immediate and register data:

(i) Register addressing mode: The registers, which is having the data to be operated is specified in the instruction.

• The IP content is,  [IP]new = [IP]old + 000AH.
• The effective address is, [EA] = [IP]new + 000AH.
• The base address is, BA = [CS] x 1610
• The memory address is, MA = [EA] + [BA].
• Program control jump into the new MA.

(5) Implied Addressing:

• The instruction itself is having the data to be operated.
• Eg. : CLC – It clears the carry flag.